1. Field of the Invention
The invention relates to identifying repetitive patterns in a design layout to simplify processes, such as optical proximity correction (OPC), verification, or contour generation. Pattern identification using segments can significantly improve processing speed compared to more macro-level identification and can be combined with more macro-level identification approaches, such as those that identify repeated cell instances or geometry-based macro blocks.
2. Description of the Related Art
Optical proximity correction (OPC) applies systematic changes to geometries of the layout to improve the printability of a wafer pattern. Specifically, as the size of integrated circuit features drops to 0.18μ and below, the features can become smaller than the wavelength of the light used to create such features, thereby creating lithographic distortions when printing the features onto the wafer. These lithographic distortions can represent significant impacts on device performance.
Rule-based OPC can include rules to implement certain changes to the layout, thereby compensating for some lithographic distortions. For example, to compensate for line-end shortening, rule-based OPC can add a hammerhead to a line end. Additionally, to compensate for corner rounding, rule-based OPC can add (or subtract) serif shapes from outer (or inner) corners. These changes can form features on the wafer that are closer to the original intended layout.
In model-based OPC, a real pattern transfer can be simulated (i.e. predicted) with a set of mathematical formulas (i.e. models). In model-based OPC, the edges of a feature in a layout can be dissected into a plurality of segments, thereby allowing these segments to be individually moved to correct for proximity effects. The placement of the dissection points is determined by the feature shape, size, and/or position relative to other features. In some embodiments, a fixed dissection length can be used for edges, e.g. every N nm. In other embodiments, multiple dissection lengths are provided, e.g. inner corner, outer corner, etc. In yet other embodiments, dissection points can be determined by exploring the optical and resist proximity behavior along the edges based on simulation or wafer results.
Verification is a process that also applies models to simulate the wafer images of the given pattern. However, instead of “correcting” the features as in model-based OPC, verification merely predicts the printed images and then compares them against the intended features, thereby providing a quantitative evaluation of the quality of the printing. Instead of providing a complete dissection of the features (as in model-based OPC), verification samples the features by selecting certain points or segments on the features on which to determine critical dimension (CD) errors (i.e. the deviation of the predicted printed images from the intended features). Note that the points or segments may coincide with the evaluation points or dissection segments of model-based OPC, or may be more fine or coarse depending on requirement. The CD error information provides a quantitative measure on the magnitude of lithographic distortions, thereby facilitating the evaluation of their severity. Generally, verification can be applied to pre-OPC and/or post-OPC layouts. As the circuit features ever increasingly drop deeper into sub-wavelength level, verification is becoming an increasingly important process.
Contour generation is a process of visualizing the printed images. This process, like verification, also samples the features at certain points or segments. However, instead of discrete CD errors, contour generation can generate sampled printed images and interpolates them to a continuous contour, which can be graphically displayed to provide a direct visualization of the printed images. Due to its similar sampling methodology, contour generation can be generically considered a type of verification process.
Because lithographic distortions can depend on many factors, including the density, size, and location of nearby features on the layout as well as photoresist parameters, the time to process this information can be considerable. Moreover, in light of this processing complexity, the tools to properly implement OPC or verification, especially model-based, are typically expensive. Therefore, a need arises for reducing the volume of information to be processed, thereby allowing the tools to more quickly process additional layouts.
Fortunately, design layouts for integrated circuits can be intrinsically repetitive. These repetitions can include shapes (i.e. polygons that represent certain geometrical features of the integrated circuit) or cells (e.g. predefined groups of shapes that may provide a certain functionality or represent repeating geometries). Identifying repetitions can be used in reducing the volume of information in the layout that needs to be processed. For example, once a repeating unit (e.g. a cell, or an area within a cell or across multiple cells) is identified, determining how to process the unit need only be done once for that cell.
However, layout hierarchies are usually function based, not geometry based. Therefore, repeating patterns or geometries may exist within a cell or among different cells that are not captured by the layout hierarchy. Moreover, if a hierarchical layout is flattened, then there is only one cell that represents the entire layout and all hierarchical information is lost.
Current methods for identifying repeating patterns have been cell-based or at most geometry-based. Unfortunately, the granularity of either identification method for OPC or verification may still be too coarse for commercial application. Therefore, a need arises for an improved pattern identification method and system.